Effect of phase of noise on the performance of 6T SRAM cell
نویسندگان
چکیده
In this paper a detailed study of the effect of the phase of noise has been done on 6T SRAM cell. The 6T SRAM has been subjected to different combinations of noises at the storage nodes and the read ability and write ability of the SRAM cell is examined considering different noise voltage levels. It is found that the effect is different under different combinations of the phases of the noise voltages.
منابع مشابه
Static-Noise-Margin Analysis of Modified 6T SRAM Cell during Read Operation
As modern technology is spreading fast, it is very important to design low power, high performance, fast responding SRAM(Static Random Access Memory) since they are critical component in high performance processors. In this paper we discuss about the noise effect of different SRAM circuits during read operation which hinders the stability of the SRAM cell. This paper also represents a modified ...
متن کاملDesign and Verification of Low Power SRAM using 8T SRAM Cell Approach
SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. Advances in chip designing have made possible the design of chips at high integration and fast performance. Lowering power consumption and increasing noise margin have become two central topics in every state of SRAM designs.The Conventional 6T SRAM cell is very much pr...
متن کامل12th Int'l Symposium on Quality Electronic Design
Bias Temperature Instability (BTI) causes significant threshold voltage shift in MOSFET using Hafnium-dioxide (HfO2) High-k dielectric material. Negative BTI and Positive BTI are two types of BTI effects observed in p-channel and n-channel MOSFET. BTI affects the stability and reliability of conventional six transistor (6T) SRAM design in nano-scale CMOS technology. Eight transistor (8T) and Te...
متن کاملAnalysis of Leakage Current and SNM For 7T SRAM Cell in Nanometre Era
: In the microprocessors world SRAM play a vital role, but as the technology is scaling in nanometer, leakage current and leakage power both are the most known problems for SRAM cells in low power applications. More than 40% of the total power of the SRAM is waste due to the leakage through transistor. This paper compares the working, performance and results of two different SRAM topologies; a ...
متن کاملA Sub-threshold 9T SRAM Cell with High Write and Read ability with Bit Interleaving Capability
This paper proposes a new sub-threshold low power 9T static random-access memory (SRAM) cell compatible with bit interleaving structure in which the effective sizing adjustment of access transistors in write mode is provided by isolating writing and reading paths. In the proposed cell, we consider a weak inverter to make better write mode operation. Moreover applying boosted word line feature ...
متن کامل